1. Field of the Invention
The present invention relates to the field of data transfer. More particularly, the present invention relates to the architecture of an address translation unit that is implemented within network logic and a method of using the address translation unit.
2. Description of Art Related to the Invention
For over a decade, a number of system architectures have been developed with input/output ("I/O") devices accessing main memory through direct virtual memory accesses ("DVMAs") using virtual addresses, instead of direct memory accesses ("DMAs") using physical addresses. One advantage associated with DVMA systems has been the simplification of data accesses by the I/O device. For example, I/O devices accessing memory through DMAs ("DMA I/O devices") must be controlled to "scatter" (i.e., allocate) data to a number of potentially discontiguous physical pages as well as to "gather" data. Gathering data that exceeds one page in length is normally accomplished by accessing a group of potentially discontiguous physical pages. In contrast, I/O devices that access main memory through DVMAs ("DVMA I/O devices") do not require such control because data accesses are made through contiguous virtual pages.
Although the DVMA systems simplified this "scatter-gather" problem, these systems required that the virtual addresses issued by the DVMA I/O devices be translated into physical addresses before data could be accessed from main memory. As shown in FIG. 1, a conventional DVMA system 100 utilizes an I/O Memory Management Unit ("I/O MMU"), sometimes referred to as an I/O Translation Lookahead Buffer 110, to translate virtual addresses to physical addresses utilized by main memory 120. As shown, the I/O MMU 110 is implemented within a bridge element 130 that couples an I/O bus 140 and a system bus 150. Normally, the I/O MMU 110 is often configured to contain a limited number "r" of address mappings (e.g., 16 fully-associative entries) to increase system performance with minimal additional costs. Thus, a plurality of I/O DVMA devices 160.sub.1 -160.sub.i ("i" being a whole number, i.gtoreq.2) are restricted to collectively use at most "r" virtual pages without mitigating system performance. If a requested address mapping is not contained within I/O MMU 110, resulting in an I/O MMU "miss", then I/O MMU 110 must engage in a table walk in order to obtain (fetch) the requested address mapping from main memory 120 which contains all potential address mappings. "Table walking" is defined as utilizing sequentially indexed tables in memory in order to find a particular translation. Thus, it may take the I/O MMU 110 much longer to execute a transaction when there is an I/O MMU "miss" compared to a "hit." Thus, overall system 100 performance is degraded when the frequency of I/O MMU misses is high.
With the emergence of multi-media communications, networks are now being required to support multiple data types. As a result, network manufacturers are tending to concentrate their efforts toward asynchronous transfer mode ("ATM") networks. In ATM networks, a large number of virtual channels, perhaps tens or hundreds, can be in operation simultaneously. Hence, if the DVMA system 100 is configured to support an ATM network coupled to I/O network interface logic 170, it would experience significant performance degradation caused by excessive fetching of address mappings from main memory. For example, an ATM link intended to sustain 622 megabits per second ("Mbs") unidirectional may decrease to a rate considerably less than 622 Mbs because of the Network Interface Logic's inability to transfer data to or from memory at that rate with excessive I/O MMU "misses" and resulting table walks.
Hence, it would be advantageous to develop an address translation unit ("ATU") implemented within and operating in cooperation with a Network Interface Card ("NIC") coupled to the I/O bus 140 such that the need for I/O MMU 110 to engage in table walking is mitigated. The NIC is used to interconnect the ATM network environment to the DVMA system.